Memory fail analysis device in semiconductor memory test system

ABSTRACT

A memory fail analysis device for a semiconductor test system is attained in which fail data of a plurality of bits is read out in parallel to count the overall fail bits in a short period of time. In a fail bit counting device in a fail memory for the semiconductor memory test system, a fail memory block 358 is provided which is recognized as a single memory when measuring the MUT while divided into M blocks to read the stored data in M bits parallel at the same time when counting the number of fail bits. Further, a fail counter 360 is provided which receives the M bit data and encodes the number of either high or low logic levels in the data into binary code data and counts the binary code data to accumulate the counted number.

TECHNICAL FIELD

This invention relates to a fail bit counting device to be used for failbit analysis of a memory device under test (hereinafter "MUT") in asemiconductor memory test system.

BACKGROUND ART

In a memory device having a redundancy and repair capability, an innercircuit for column and low addresses includes, in addition to X and Yaddress lines, one or more address lines in each of the X and Y addressdirections for the purpose of repair. These additional address lines areused for being replaced with defective address lines through a lasertrimming process whereby improving yield of the memory devices.

A semiconductor test system performs various types of operational margintests such as a supply voltage margin test or an access time test. It isan important test item for counting the number of fail bits of the MUTunder these tests. For example, in testing a semiconductor wafer, waferproduction steps may vary depending on the number of fail bits. If thenumber of fail bits is greater than the predetermined amount, it isdetermined that the device is defective and the production process isterminated since it is not repairable. If the number of fail bits issmaller than the predetermined amount, the device is considered to berepairable. Thus, a fail counter is employed in the test system to countthe overall fail bits of the MUT.

FIG. 4 shows a basic configuration of such a memory test system.

During the test, output signals from a plurality of MUTs are comparedwith expected data from a PDS (programmable data selector) 60 by a DC(digital comparator) 75, and the resultant pass/fail information77_(fail) is stored in an AFM (address fail memory) 200 in an FM (failanalysis memory) 90. After the test, the AFM 200 reads out the storedinformation for carrying out the fail analysis.

In the AFM 200, as shown in FIG. 5, it is structured to have a pluralityof channels Q in parallel to count the overall fail bits forcorresponding MUTs.

Each AFM 200 includes a controller 210, an address pointer 220, an MUX(multiplexer) 230, an MUX 240, a fail memory 250, and a fail counter260.

The fail memory 250 has a storage memory having at least the sameaddress capacity as that of the MUT. The fail memory 250 is used,firstly, during the memory test process, to store therein the Pass/Faildata which is resulted from comparing the outputs of the MUT with theexpected data by the DC 75. Address signals from a PG (patterngenerator) 50 is used as the address information for this process.

Secondly, in the fail analysis process, the data in the fail memory 250is read out to count the overall number of fail bits. In this situation,by switching the MUX 230, the address information for reading the datain the fail memory 250 is provided from the controller 210 through theaddress pointer 220. All of the addresses are sequentially generated andthe fail bits are counted by the counter 260. In this example, the failcounter 260 is a type of counter which counts up when the fail data is"1".

The controller 210, in receiving fail analysis parameters from a CPU,controls the address generation sequence for counting the number of thefail bits. The address pointer 220 generates address signals to besupplied to the fail memory 250. The address pointer 220 generates theaddress signal by counting up for a desired bit area in an N bit addresssignal and provides the generated address signal to the MUX 230.

The MUX 230 is a selector which, in receiving a select signal from thecontroller 210, outputs the address signals from the PG 50 during themeasurement while outputs the address signals from the address pointer220 during the fail analysis.

The MUX 240 is a selector to select address signals 242_(adr) to besupplied to the fail memory 250 in a manner that the fail memory 250 hasthe same address space as that of the MUT. For example, the MUX 240provides the address signal in which unused upper addresses are set tozero.

The foregoing is the explanation of the basic structure of the AFM 200.The counting operation in the AFM 200 is explained in the following withreference to the drawings.

FIG. 6 shows an example of data stored in the fail memory 250 when thenumber of address bits of the MUT is eight, and the X and Y addressesare provided to the fail memory 250 in which the X address is 4 bits andthe Y address is 4 bits.

In the example of FIG. 6, to count all of the fail data, the address (X,Y) is sequentially incremented from (0, 0) to (F, F) to access all of256 addresses while counting the number of fail data. In this example,the counted number is "18". Because it is necessary to apply all of theaddresses to the fail memory and read the fail data therefrom, it takesa long time for counting the number which is proportional to thecapacity of the memory. Thus, it requires a long time for counting thefails in a large scale memory device.

As noted above, to count all of the fail data, it is necessary to applyall of the addresses to the fail memory and read the fail data therefromfor counting up the fail data. Thus, it takes a time for counting thefails in proportion to the capacity of the memory device, whichadversely affects a test throughput in the device testing for largecapacity memories such as 64M bit or 250M bit memory devices.

Therefore, it is an object of the present invention to provide countingmeans which is capable of reducing the time for counting the number offail bits by reading out the data from the fail memory in a plural bitform at the same time and counting the fail bits in parallel at the sametime.

SUMMARY OF THE INVENTION

In a fail bit counting device for a fail memory to be used for asemiconductor memory test system, it is provided a fail memory block 358which is recognized as a single memory when measuring the MUT whilebeing divided into M blocks to read the stored data in M bits parallelat the same time when counting the number of fail bits. Further, a failcounter 360 is provided which receives the M bit data and encodes thenumber of either high logic or low logic in the data into binary codedata and counts the binary code data to accumulate the counted number.

In this arrangement, a memory fail analysis device for a semiconductortest system is attained in which fail data of a plurality of bits isread out in parallel to count the overall fail bits in a short period oftime.

The fail counter 360 includes an encoder 362 which converts the numberof either high logic or low logic levels in the data received from the Mblocks of the fail memory block 358 to binary code data, a countregister 366 which latches the accumulated data, and an accumulator 364which accumulates the encoded data from the encoder 362 and the datafrom the count register 366.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing structures of a fail memory 350 and afail counter 360 of the present invention in which the number of overallfail bits is counted in a 4 bit parallel manner.

FIG. 2 is a block diagram showing a fail counter 360 of the presentinvention corresponding to one channel of the memory test system.

FIG. 3 shows a logic data code conversion table for an encoder of thepresent invention which converts the received data to binary codes.

FIG. 4 shows an example of structure in a memory test system.

FIG. 5 is a block diagram showing an example of structure in aconventional AFM (address fail memory) 200 for counting the number ofoverall fail bits of an MUT (memory under test).

FIG. 6 is a diagram showing an example of data stored in a fail memoryfor explaining the fail counts in the conventional technology where thenumber of address bit is eight.

FIG. 7 is a diagram showing the data in a single memory space forwriting the data therein in comparison with the data divided into fourmemory blocks for reading the data in accordance with the presentinvention.

FIG. 8 is an example of bit assignment for selecting the memory blocksin the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention is explained with an example fordividing a fail analysis memory into 4 memory blocks and reading thestored data by 4 bits at the same time for counting the number of failbits. The address data in this example is formed with 8 bits as in theconventional example of FIG. 6.

In the present invention, in testing the MUT, the fail information isstored in a fail memory block 358 as a single memory in a manner similarto the conventional technology. In the fail analysis process, however,the fail data is read out in 4 bit parallel at the same time forcounting the number of fail bits.

FIG. 1 shows a circuit arrangement of fail counting means correspondingto one channel of the memory test system in accordance with the presentinvention. This circuit arrangement is formed of a fail memory and afail counter for counting the overall fail bits in a manner of 4 bitparallel.

FIG. 8 shows an example of assigning bits for selecting blocks in thefail memory.

As shown in FIG. 1, the fail memory 350 is formed of a decoder 352, anOR gate 356 and a fail memory block 358.

The fail memory block 358 has a structure in which the fail memory isdivided into four memory blocks. First, in the measurement of the MUT, amemory control register 354 is set to "0" so that each of enableterminals CE of the memory blocks will not be set to an enable state.Under this situation, upper address bits A6 and A7 are provided to thedecoder 352. One of the terminals CE of the memory blocks is enabled byone of the four outputs of the decoder 352. Thus, the data writingoperation is carried out for a single memory as in the conventionaltechnology. FIG. 7 shows a memory address space in this situation. InFIG. 7, Y addresses 0-3 are assigned to a memory block 1, Y addresses4-7 are assigned to a memory block 2, Y addresses 8-B are assigned to amemory block 3, and Y addresses C-F are assigned to a memory block 4,respectively.

Second, in the memory fail analysis process, the memory control register354 is set to "1". Each of the outputs of the register is provided tothe corresponding OR gate 356, which sets all of the enable terminals CEof the memory blocks to the enable state. As a result, the four memoryblocks are readable in parallel at the same time. Under this situation,lower bit addresses A0-A5 are sequentially provided to the memory blocksto read the data in the corresponding addresses.

FIG. 2 shows a structure of the fail counter 360 for corresponding toone channel of the memory test system. The fail counter 360 is formed ofan encoder 362, an accumulator 364 and a count register 366.

The encoder 362, in receiving the 4 bit data from the fail memory block358, converts the number of "1" data to binary code data consisting of 3bit (for indicating 0-4). The logic data conversion table in the encoder362 is shown in FIG. 3.

The accumulator 364 accumulates the encoded data from the encoder 362and the data from the count register 366 and outputs the resultant datawhich is latched in the count register 366. The count register 366 is alatch register which is able to express and hold at least the equalnumber of bits of the memory capacity. The count register 366 is clearedprior to the of the operation.

Under the fail counting process of the present invention, the addressgeneration sequence is reduced to 1/4, and thus the time required forcounting the fail bits is also reduced to 1/4 of the conventionaltechnology.

In the foregoing embodiment, the present invention is explained by theexample in which the fail analysis memory is divided into 4 memoryblocks. However, the fail analysis memory may be divided into arbitrarynumber of memory blocks M (for example, 16, 32 or 64) while accompanyingan encoder, an accumulator and a count register having correspondingstructures to meet the number of memory blocks and accomplish theeffects of the present invention.

Since it is configured as described in the foregoing, the presentinvention has the following effects.

The fail memory block 358 is provided in which the fail memory isdivided into M memory blocks to read the data therefrom at the sametime. During the measurement of the MUT, the fail memory block 358 istreated as a single memory and the data is written therein. During thefail analysis, the memories of all of the M memory blocks are set to theenable state so that the M memory data is read out in parallel at thesame time. The read out data is converted to the binary code data by anencoder and accumulated to count the number of fails. As a result, theaddress generation process and the time for counting the fails arereduced to 1/M of the conventional technology.

What is claimed is:
 1. A fail analysis device for a semiconductor memorytest system to evaluate performance of an MUT (memory under test),comprising:a pattern generator for generating a test pattern signalincluding MUT address data to be supplied to said MUT in a fail dataacquisition process; a fail memory for storing fail data of said MUT asa single memory in said fail data acquisition process, said fail memorybeing formed with a plurality of memory blocks which are accessed inparallel at the same time in a fail data analysis process; an addresspointer for generating fail memory address data in said fail dataanalysis process; a multiplexer for applying said MUT address data tosaid fail memory in said fail data acquisition process and applying saidfail memory address data to said fail memory in said fail data analysisprocess; enable signal providing means for providing an enable signal toonly one of said plurality of memory blocks of said fail memory in saidfail data acquisition process and providing an enable signal to all ofsaid plurality of memory blocks in said fail data analysis process; anda fail counter for counting the number of fail data in said fail memorywhen receiving said fail data from said plurality of memory blocks inparallel, said fail counter including an encoder for converting thetotal number of said memory blocks having said fail data therein to abinary code representing said total number.
 2. A fail analysis devicefor a semiconductor memory test system as defined in claim 1, whereinsaid fail counter further including an accumulator which adds saidbinary code from said encoder to data from a count register whichlatches added results until the next count cycle of said fail counter.3. A fail analysis device for a semiconductor memory test system asdefined in claim 1, wherein said encoder in said fail counter is a datatable for converting the total number of said memory blocks in said failmemory having said fail data therein to a binary code representing saidtotal number.
 4. A fail analysis device for a semiconductor memory testsystem as defined in claim 1, wherein said enable signal providing meansincludes a decoder for decoding higher bits of address data generatedfor said fail analysis process to produce said enabling signal and aplurality of gate circuits for selectively providing said enable signalto one of said memory blocks through one of said gate circuits in saidfail data acquisition process while providing said enable signal to allof said memory blocks through all of said gate circuits in said failanalysis process.